The present invention relates to logic circuit design, and more specifically, to systems and methods for specifying circuit level connectivity during logic circuit synthesis without modifying the logic level description.
VLSI design methodologies, as well as various other approaches to complex designs, employ levels of abstraction to limit complexity during steps in the design process. Synthesis is a common approach to VLSI design that converts a higher level abstraction into a lower, more detailed, level of abstraction. While there are various types of synthesis, typical synthesis processes convert a logic level description of a design into a circuit level description. Human designers can influence synthesis by modifying the logic description while maintaining the same functionality. Often these modifications expand the level of detail in the logic description. However, modifying the logical level to influence the circuit level can reduce the clarity of the logic to human designers and can require re-verification to ensure the new logic is functionally correct. In addition, designs are often owned and implemented by separate designers at the logic and circuit level. For example, a logic designer may code and own the logic level description, while a circuit designer implements and owns the design at the circuit (either via synthesis or custom design).
The synthesis processes are typically implemented as CAD (computer-aided design) software and require little human intervention. In contrast, a custom VLSI design methodology requires a human designer to perform the expansion of details from the logic level to circuit level. Although the automation of synthesis provides an inherent productivity advantage, there are some scenarios in VLSI design where experienced human designers can produce better results. Thus, it would be desirable if human designers could control portions of the synthesis process.